It is common in the semiconductor field to test and analyze defective chips in order to pinpoint the cause of a problem. Various types of failure analysis (FA) tools have been developed to examine/inspect the device under test (DUT) and pinpoint the location or region on the DUT where the problem occurs from photon emission or secondary electron acquisition or physical probing, etc. For example, some FA tools known in the art include EMMI (Emmission Microscopy), pico-probe stations, IDS (electron beam prober) and sem (electron microscope). While the DUTs are physically being viewed by one of these tools, the FA tools require physical access to the DUT for purposes of viewing the die surface and, in the case of a pico-probe station, to physically probe the DUT. This examination of the DUT is therefore done in a lab where the FA tools are located.
However, in addition to evaluating the DUT by physically inspecting the regions of the chip while signals are applied to the DUT, faults in a DUT are also pinpointed by simply applying signals to the pins or certain test nodes on the DUT and analyzing the output signals from the output pins of the chip. This type of analysis is thus purely electrical in nature and involves the generation of test vector pattern data that is fed into the chip. The test vectors are applied to the chip by a tester, which is depicted in the system block diagram of FIG. 1 by reference numeral 100. Typically the program that comprises the test vector pattern is loaded from a server 102 where the program is stored, and access is commonly provided to a user (the test engineer) at a client station 104 (typically a personal computer (PC)) The tester 100 is provided with a test head, which includes a motherboard 108 with a socket 106 for supporting the DUT. The test head typically contains a high speed DRAM buffer for loading input data and output data. The DUT 110 is shown in FIG. 1, mounted in the socket 106. In the case of a packaged device with 18 I/O or clock pins, 18 electrical connections will typically have to be made between the mother board 108 and the socket 106 on which the device under test 110 (DUT) is mounted. Output data from the output pins of the DUT is sent to the tester 100 and can be analyzed by the user at the client 104, which is connected to the tester 100, typically via an intranet connection.
In practice, the tester on which the DUT is mounted is commonly placed on top of the FA tool (e.g. in the case where the DUT has to be placed in a vacuum chamber of the FA tool) or in close proximity to the FA tool (e.g., in the case where the FA tool comprises a microscope for viewing the DUT). One such FA tool/tester combination is shown in FIG. 2, which shows a tester 200 with its motherboard, 202 and socket 204, supporting a DUT 206. Mounted over the tester 200 is an FA tool 210 in the form of a microscope. This close proximity causes problems for the analysis done using the FA tool since, the tester with its many data lines and cooling equipment causes a fair amount of vibration, which interferes with the FA tool analysis. In fact, it is not uncommon for a DUT to have many more than just 18 pins. Typical testers may have sockets with 512, 756, or 1024 I/O pins and an equivalent number of data lines between the motherboard and the socket.
The present invention seeks to address this problem.
Furthermore, even if the test engineer who ultimately performs the test is remotely located at a client station such as client 104 shown in FIG. 1, the systems known in the art still require a person to be present in the lab to place the DUT in the tester even in the absence of FA tool analysis, if the DUT is simply being electronically tested using test vectors.
The present invention seeks to provide a more convenient solution in cases where chips are tested purely electronically by means of test vector pattern data.